1. Field of the Invention
The present invention relates to a system for sharing a plurality of downstream information processing apparatuses such as a plurality of I/O equipment among a plurality of upstream information processing apparatuses such as CPUs and a method used to the system, and particularly, to an I/O equipment sharing system which a plurality of CPUs and a plurality of I/O equipment are connected through a network and a method used to the I/O equipment sharing system.
This application is based upon and claims the benefit of priority from Japanese patent application No. 2006-254366, filed on Sep. 20, 2006, the disclosure of which is incorporated herein in its entirety by reference.
2. Related Art
At present, a peripheral component interconnect (PCI) is widely used as a bus standard for connecting between respective parts in a computer. A PCI Express is standardized as a next generation standard of the PCI. The PCI Express increases a communication capacity by changing a conventional parallel bus to a serial bus and carrying out communication by a packet system accompanied with switching.
However, the PCI Express permits only a tree-like arrangement in which a plurality of I/O equipment 108-1 to 108-3 are connected to one CPU 101 as shown in FIG. 1. In FIG. 1, the CPU 101 is connected to a route complex 102, and the route complex 102 is connected to the I/O equipment 108-1 to 108-3 through a PCI Express switch 1601. The PCI Express switch 1601 includes an upstream PCI-PCI bridge 1602 and downstream PCI-PCI bridges 1604-1 to 1604-3, the upstream PCI-PCI bridge 1602 is connected to the downstream PCI-PCI bridges 1604-1 to 1604-3 through a PCI Express switch internal bus 1603. The route complex 102 is connected to a memory 103.
On the other hand, conventionally, when a plurality of I/O equipment are shared among a plurality of CPUs, the advanced switching interconnect (ASI), in which a plurality of CPUs and a plurality of I/O apparatuses are connected to a network in a dispersed state, is standardized as shown in “ASI Core Architecture Specification Rev. 1.1, ASI-SIG, November, 2004”.
With reference to FIG. 2, CPUs 101-1 and 101-2 are connected to route complexes 102-1 and 102-2, respectively, and the route complexes 102-1, 102-2 are connected to I/O equipment 108-1 to 108-3 through an ASI network 1701. The route complexes 102-1, 102-2 are connected to memories 103-1, 103-2, respectively.
The ASI network 1701 includes route complex side PC Express-ASI bridges 1702-1 and 1702-2, an ASI switch 1703, a fabric manager 1704, and I/O equipment side PCI Express-ASI bridges 1705-1 to 1705-3.
The route complex side PCI Express-ASI bridges 1702-1 and 1702-2 are connected to the route complexes 102-1 and 102-2, and have a function for encapsulating a TLP (Transaction Layer Packet) in an ASI packet and carrying out transmission and reception. The ASI switch 1703 carries out switching so that the ASI packet, which encapsulates the packet (TLP) of the PCI Express, is transferred to a port of the destination of the ASI packet. The I/O equipment side PCI Express ASI bridges 1705-1 to 1705-3 are connected to the I/O equipment 108-1 to 108-3 and have a function for encapsulating a TLP in an ASI packet and carrying out transmission and reception. A fabric manager 1704 manages an inter-bridge connection in the route complex side PCI Express-ASI bridges 1702-1, 1702-2 and the I/O equipment side PCI Express-ASI bridges 1705-1 to 1705-3.
FIG. 3 shows a routing method in the ASI network 1701. In FIG. 3, the same components as the structure components those as shown in FIG. 2 are denoted by the same reference numerals. In the ASI, routing is carried out by a source routing method. In the method, a packet is transferred to a destination by using relative position information from a transmission source. Further, in the management method of I/O equipment 108-1 to 108-3 in the ASI, a fabric manager 1704 holds the routing information of all route complexes 102-1 and 102-2, ASI switches 1703-1 to 1703-3 and the I/O equipment 108-1 to 108-3, and manages a plurality of ASI address spaces. And the plurality of I/O equipment 108-1 to 108-3 can be managed by setting a source routing path of each ASI address space by a manager who operates the fabric manager 1704.
As a technology relating to the present invention, FIG. 1 of Japanese Patent Application Laid-Open Publication (JP-A) No. 10-49482 discloses a system in which one or at least two processors, a first bridge, a second bridge, and a plurality of peripheral devices are connected through a bus, respectively, (a bus for connecting a first bridge and a second bridge, and a bus for connecting the second bridge and the plurality of peripheral devices are a PCI bus). Further, JP-A No. 10-178442 discloses a system for allocating each one VLAN ID to each terminal, managing by a table, and controlling a connection between terminals.
Further, other technology relating the present invention is disclosed in “Protocol Interface #8 (PI-8) R1.0, ASI-SIG, February, 2004”.
However, when an ASI is used between a plurality of CPUs, there are two disadvantages.
A first disadvantage resides in that it is complex to carry out a group management of a plurality of I/O equipment, and thereby expandability is restricted. This is because, when the group management of the plurality of I/O equipment is carried out in the ASI, a fabric manager is required to hold all the routing information and further a routing path must be set to each of ASI address spaces of the I/O equipment 108-1 to 108-3.
A second disadvantage resides in that N-fold redundancy cannot be easily set to the same I/O equipment. This is because when a plurality of the same I/O equipment make a different response, they are out of synchronization and cannot be operated, in addition to the reason of the first disadvantage.
Accordingly, an object of the present invention is to provide a system for and a method of easily carrying out setting for sharing a plurality of CPUs and a plurality of I/O equipment while increasing redundancy.